SCRATCH REDUCTION IN SEMICONDUCTOR CIRCUIT FABRICATION USING CHEMICAL-MECHANICAL POLISHING
Коммуникация, связь, радиоэлектроника и цифровые приборы
A relatively hard polishing padis used first to planarize the wafer surface using a chemically reactive and abrasive slurry. A second polishing step is then carried out on a relatively soft polishing pad using a slurry to remove or reduce scratches introduced by polishing with the hard pad.
SCRATCH REDUCTION IN SEMICONDUCTOR CIRCUIT FABRICATION USING CHEMICAL-MECHANICAL POLISHING
A process for polishing a layer on a semiconductor wafer in which the incidence of undesirable scratches on the polished surface is reduced by using a multiple step polishing procedure. A relatively hard polishing padis used first to
planarize the wafer surface, using a chemically reactive and abrasive slurry. A second polishing step is then carried out on a relatively soft polishing pad, using a slurry to remove or reduce scratches introduced by polishing with the hard pad. A final polishing step is performed on the soft polishing pad using de-ionized water to remove particles from the surface of the wafer.
This is a continuation of application Ser. No. 08/512,771, filed Aug. 9, 1995, now abandoned.
FIELD OF THE INVENTION
when forming the metal layer into the desired circuit inter connections. The resulting filaments of metal remaining in the CMP scratches after forming the interconnections can cause a short circuit fault to occur if the scratch is proximate
5 to contacts or interconnection lines in the metal layer.
Thus, what is required is a chemical-mechanical polishing process in which scratches on the wafer surface are avoided or removed prior to deposition of a subsequent conductive layer.
This invention relates to the production of semiconductor 10 integrated circuits, and more specifically to a process for manufacturing integrated circuits in which scratches due to chemical-mechanical polishing are reduced.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is pro vided a process for planarizing a layer formed on a wafer during fabrication of a semiconductor integrated circuit. A
BACKGROUND OF THE INVENTION
Modern ultra-large scale integrated (ULSI) circuits are constructed with up to several millions of active devices, such as transistors and capacitors, formed in a semiconduc tor substrate. Interconnections between the active devices are created by providing a plurality of conductive intercon nection layers, such as polysilicon and metal, which are etched to form conductors for carrying signals between the various active devices. The individual interconnection layers are nominally electrically isolated from one another, and from the silicon substrate, by an insulative interlayer dielec tric (ILD), such as silicon dioxide (Si02) produced by chemical vapor deposition (CVD). The conductive layers and interlayer dielectric are deposited on the silicon sub strate wafer in succession, with each layer being, for example, of the order of 1 micron in thickness. The ILD conformably covers the underlying layer (e.g. a metal layer etched to form conductive interconnects) such that the upper surface of the ILD is characterized by a series of non-planar
steps which correspond in height and width to the underly ing interconnect lines.
These height variations in the upper surface of the ILD can have deleterious effects on the subsequent steps and layers applied in forming the integrated circuit. For example,
15 first polishing step of the process involves polishing the wafer on a first polishing pad using a slurry having a
chemical reagent and a suspension of abrasive particles. The first polishing pad is a relatively hard pad (relatively low compressibility) and is used to abrade a surface portion of
20 the layer so as to planarize the surface of the layer. A second polishing step of the process is then performed on a second polishing pad, also using a slurry. The second polishing pad
is a relatively soft pad (relatively high compressibility), and is used to remove scratches from the planarized layer surface
25 which may have resulted from the first polishing step.
Finally, a third polishing step is performed on the wafer
using the second polishing pad but de-ionized water instead of the abrasive slurry. The third polishing step removes the slurry solution and particles from the surface of the wafer.
30 In order to abrade the surface of the layer being planarized, the pressure used to apply the wafer to the first polishing pad is relatively high, and is preferably in the range of about 3.5 to about 9 pounds-per-square-inch (PSI). The scratch removal phase comprising the second polishing
35 step involves less pressure between the wafer and the second polishing pad, in the range of about 2 to about 5 PSI. Finally, the rinsing stage comprising the third polishing step involves the least pressure, and is preferably of the order of 0.5 to 1.5 PSI.
a non-planar dielectric surface can interfere with the optical 40
resolution of subsequent photolithographic processing steps.
This can make the high resolution lines required for compact ULSI circuits difficult to produce. Additionally, if the height variations in the ILD surface are severe, there is a danger that insufficient metal coverage can occur at the step height 45
variations in the subsequent conductor layer, which can
result in open circuit flaws.
In order to combat these difficulties, various techniques have been developed in an attempt to better planarize the upper surface of the ILD. One approach, referred to as 50 chemical-mechanical planarization or polishing (CMP), employs abrasive polishing to remove the surface height variations of the dielectric layer. According to this method
the semiconductor wafer is pressed against a moving pol ishing surface that is wetted with a chemically reactive, 55 abrasive slurry. Slurries are usually either basic or acidic and generally contain a suspension of alumina or silica particles. The polishing surface and wafer are moved relative to one another in an abrasive fashion to remove protruding portions
of the dielectric layer. The abrasive polishing process con- 60
tinues until the surface of the ILD is largely flattened.
One problem which has been encountered with subjecting semiconductor wafers to chemical-mechanical polishing is that scratches can be produced on the polished surface of the wafer (e.g. on the surface of the ILD). Metal deposited on 65 the ILD as the next layer of the integrated circuit fills these scratches, but can then be difficult to remove therefrom
Rotation of both the polishing pad and the wafer is employed for each of the polishing steps, with rotation speeds typically in the range of about 10 to 20 revolutions per-minute (RPM) for the first and second polishing steps. The third polishing step is preferably carried out with higher rotational speeds, such as greater than 30 RPM for each of the polishing pad and the wafer. In the preferred embodi- ments the third polishing step involves rotational speeds of the order of 60 RPM which facilitates cleansing of the wafer of slurry and abraded particles with the aid of the supplied water.
The wafer is polished on the first polishing pad to remove a desired amount of material from the layer being polished, and the time required for polishing during the first polishing step is adjusted accordingly. For example, for many appli cations the first polishing step time will be in the range of about one minute to about four minutes. The second pol- ishing step, used for removing or reducing scratches on the wafer, generally achieves better results with longer polishing times, although it has been found that a second polishing step time in the range of about 30 to 45 seconds can yield adequate results. It is preferred that the second polishing step be performed for at least 30 seconds. The third polishing step, which is primarily for removing particles from the wafer surface with water as a rinsing agent, can be per formed for any suitable length of time, and one minute of this processing step has been found to generally be suffi- cient.
Other features and advantages of the present invention will be apparent from the appended claims, and from the detailed description of the invention which follows below.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in greater detail hereinafter, by way of example only, with reference to the accompanying drawings, wherein:
ing surface is typically a planar pad made of a porous material, such as blown poyurethane mounted on a planar rotatable platen.
FIG. 2 illustrates a semiconductor wafer 100 following
5 the CMP processing, wherein the surface features of the ILD 160 have been generally removed. A prior art polishing process may involve an initial polishing step on a relatively hard polishing pad (e.g. a polishing pad known by the name IC-60 manufactured by Radel, Inc.) using an abrasive slurry
FIG. 1 is a cross-section of a portion of a conventional 10
FIG. 2 is a cross-section of a conventional semiconductor substrate after CMP processing.
FIG. 3 is a cross-section of the semiconductor substrate
in order to abrade the surface of the ILD to a generally planar state (FIG. 2). The initial polishing step may in some instances be followed by a rinsing or buffing step in order to remove particles from the surface of the wafer which may have adhered thereto during the planarizing step. The rinsing
illustrated in FIG. 2 after a photoresist layer has been deposited.
FIG. 4 is a cross-section of the semiconductor substrate of FIG. 3 after the formation of etched contact openings.
FIG. 5 is a cross-section of the semiconductor substrate of FIG. 4 after a conductive material deposition.
FIG. 6 is a cross-section of the semiconductor substrate illustrated in FIG. 5 after the conductive material has been etched back.
FIG. 7 is a cut-away side view of a conventional chemical-mechanical polishing apparatus; and
FIG. 8 is a flowchart showing an example of the method of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
A novel chemical-mechanical polishing process for semi conductor integrated circuit formation is described. In the following description, numerous specific details are set forth, such as specific materials and process parameters, etc. in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known semiconduc tor processes and machinery have not been described in particular detail in order to avoid unnecessarily obscuring the present invention.
In FIGS. 1to 4, there is shown a cross-sectional repre sentation of a potion of a semiconductor wafer at various stages of processing according to the prior art. These figures illustrate a difficulty which can arise when scratches are formed on the surface of an interlayer dielectric (ILD) by a chemical-mechanical polishing step.
FIG. 1 shows a cross-section view of a portion of a semiconductor wafer 100 comprising a silicon substrate 120 having a polysilicon line 140 formed thereon. An insulating interlayer dielectric 160 is deposited over the silicon sub strate 120 and polysilicon line 140. The conformal nature of the ILD 160 causes the surface 180 thereof to generally reflect the uneven topography of the underlying layers. The uneven surface 180 of the ILD 160 can have disadvanta geous effects on the deposition, patterning and etching of subsequent layers. Consequently, a technique known as chemical-mechanical polishing (CMP) has been developed in order to planarize the surface of ILD 160 prior to subsequent processing. In general, chemical-mechanical polishing processes involve pressing the semiconductor wafer against a moving polishing surface that is wetted with a chemically reactive, abrasive slurry. Slurries are usually either basic or acidic and generally contain a suspension of alumina or silica particles as an abrasive agent. The polish-
15 or buffing step may be performed using a CMP apparatus and a relatively soft polishing pad (such as a SUBA IV
polishing pad from Radel, Inc.) which is supplied with water while the wafer is applied thereto. However, in some instances the chemical-mechanical polishing process of the
20 prior art can leave a scratch 200 in the surface of the polished layer, which can eventually result in a flawed semiconductor circuit as described herein below.
The next step in the process involves depositing a photo resist layer 220, and patterning the layer with openings 222
25 for the formation of interlayer contacts to the silicon sub strate 120 and polysilicon line 140 (FIG. 3). Etching of the ILD 160 is then performed according to the patterned
photo-resist 220 using, for example, a conventional dry plasma etch process. This results in the formation of etched
30 contact openings 224A, 224B and 22C, as illustrated in FIG.
4. In this example, the scratch 200 in the surface of the lLD
160 is in the region of adjacent contact openings 224B and 224C. A layer 230 of a conductive material such as tungsten is then deposited on the wafer, to fill the contact openings so
35 as to create interlayer contacts. The conductive material 230 is then removed from the surface of the ILD 160 to leave plugs of conductive material 232A, 232B and 232C forming the interlayer contacts. The removal of the conductive material 230 is performed using an etching process or a
40 polish-back process of chemical-mechanical polishing.
However, as shown in FIG. 6, the depression in the surface
of ILD 160 resulting from the scratch 200 can disadvanta geously retain a portion of the conductive material on the surface of ILD 160, causing a conductive bridge 240 short-
45 circuiting adjacent interlayer contacts 232B and 232C. This short circuit results in a flawed integrated circuit. Accordingly, it can be seen that scratches to a semiconductor wafer introduced during a chemical-mechanical polishing processing step can, in some circumstances, produce flawed
50 integrated circuits, and thereby reduce the yield of a fabri cation process.
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